Hynix HMT41GS6MFR8C-PB Datenblatt

Rev. 1.0 /Jul. 2012 1204pin DDR3 SDRAM SODIMM*SK hynix reserves the right to change products or specifications without notice.DDR3 SDRAM Unbuffered SO

Rev. 1.0 /Jul. 2012 10 4GB, 512Mx64 Module(1Rank of x8) DQS0DQS0DM0DQ[0:7]DQSDQSDMDQ [0:7]D0RASCASS0WECK0CK0CKE0ODT0240ohmZQ+/-1%RASCASCSWECKCKCKEODTA

Rev. 1.0 /Jul. 2012 11 8GB, 1Gx64 Module(2Rank of x8)8GB, 1Gx64 Module(2Rank of x8) DQS3DQS3DM3DQ[24:31]DQSDQSDMDQ [0:7]D11RASCASS1WECK1CK1CKE1ODT1A[O

Rev. 1.0 /Jul. 2012 12 Absolute Maximum RatingsAbsolute Maximum DC RatingsNotes:1. Stresses greater than those listed under “Absolute Maximum Ratings”

Rev. 1.0 /Jul. 2012 13 AC & DC Operating ConditionsRecommended DC Operating ConditionsNotes:1. Under all conditions, VDDQ must be less than or equ

Rev. 1.0 /Jul. 2012 14 AC & DC Input Measurement LevelsAC and DC Logic Input Levels for Single-Ended SignalsAC and DC Input Levels for Single-Ende

Rev. 1.0 /Jul. 2012 15 AC and DC Input Levels for Single-Ended SignalsDDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as spec

Rev. 1.0 /Jul. 2012 16 Vref TolerancesThe dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figu

Rev. 1.0 /Jul. 2012 17 AC and DC Logic Input Levels for Differential SignalsDifferential signal definitionDefinition of differential ac-swing and “tim

Rev. 1.0 /Jul. 2012 18 Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)Notes:1. Used to define a differential signal slew-rate

Rev. 1.0 /Jul. 2012 19 Single-ended requirements for differential signalsEach individual component of a differential signal (CK, DQS, DQSL, DQSU, CK,

Rev. 1.0 /Jul. 2012 2 Revision HistoryRevision No. History Draft Date Remark0.1 Initial Release Mar.2011 Preliminary0.2 Added IDD Specification Jul.20

Symbol ParameterDDR3-800, 1066, 1333, & 1600Unit NotesMin MaxVSEHSingle-ended high level for strobes (VDD / 2) + 0.175 Note 3 V 1,2Single-ended hi

Symbol ParameterDDR3-800, 1066, 1333, 1600 Unit NotesMin MaxVIX(CK)Differential Input Cross Point Voltage relative to VDD/2 for CK, CK-150 150 mV 2-17

Rev. 1.0 /Jul. 2012 22 Slew Rate Definitions for Differential Input SignalsInput slew rate for differential signals (CK, CK and DQS, DQS) are defined

Rev. 1.0 /Jul. 2012 23 AC & DC Output Measurement LevelsSingle Ended AC and DC Output LevelsTable below shows the output levels used for measureme

Rev. 1.0 /Jul. 2012 24 Single Ended Output Slew RateWhen the Reference load for timing measurements, output slew rate for falling and rising edges is

Rev. 1.0 /Jul. 2012 25 Differential Output Slew RateWith the reference load for timing measurements, output slew rate for falling and rising edges is

Rev. 1.0 /Jul. 2012 26 Reference Load for AC Timing and Output Slew RateFigure below represents the effective reference load of 25 ohms used in defini

Rev. 1.0 /Jul. 2012 27 Overshoot and Undershoot SpecificationsAddress and Control Overshoot and Undershoot SpecificationsAddress and Control Overshoot

Rev. 1.0 /Jul. 2012 28 Clock, Data, Strobe and Mask Overshoot and Undershoot SpecificationsClock, Data, Strobe and Mask Overshoot and Undershoot Defin

Rev. 1.0 /Jul. 2012 29 Refresh parameters by device densityRefresh parameters by device densityParameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb UnitsRE

Rev. 1.0 /Jul. 2012 3 DescriptionSK hynix Unbuffered Small Outline DDR3 SDRAM DIMMs (Unbuffered Small Outline Double Data Rate Syn-chronous DRAM Dual

Rev. 1.0 /Jul. 2012 30 Standard Speed BinsDDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.DDR3-800 Spee

Rev. 1.0 /Jul. 2012 31 DDR3-1066 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 34.Speed Bin DDR3-1066FUnit NoteCL - nRCD

Rev. 1.0 /Jul. 2012 32 DDR3-1333 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 34.Speed Bin DDR3-1333HUnit NoteCL - nRCD

Rev. 1.0 /Jul. 2012 33 DDR3-1600 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 34.Speed Bin DDR3-1600KUnit NoteCL - nRCD

Rev. 1.0 /Jul. 2012 34 Speed Bin Table NotesAbsolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); 1. The CL setting and CWL setting result in

Rev. 1.0 /Jul. 2012 35 Environmental ParametersNote: 1. Stress greater than those listed may cause permanent damage to the device. This is a stress ra

Rev. 1.0 /Jul. 2012 36 IDD and IDDQ Specification Parameters and Test ConditionsIDD and IDDQ Measurement ConditionsIn this chapter, IDD and IDDQ measu

Rev. 1.0 /Jul. 2012 37 Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements[Note: DIMM level Output test load condition

Rev. 1.0 /Jul. 2012 38 Table 1 -Timings used for IDD and IDDQ Measurement-Loop PatternsTable 2 -Basic IDD and IDDQ Measurement ConditionsSymbolDDR3-10

Rev. 1.0 /Jul. 2012 39 IDD2NPrecharge Standby CurrentCKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Ad

Rev. 1.0 /Jul. 2012 4 Key Parameters*SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed to match.Spee

Rev. 1.0 /Jul. 2012 40 IDD4ROperating Burst Read CurrentCKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Comm

Rev. 1.0 /Jul. 2012 41 a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00Bb) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom

Rev. 1.0 /Jul. 2012 42 Table 3 - IDD0 Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.b) DQ signals are MID-LE

Rev. 1.0 /Jul. 2012 43 Table 4 - IDD1 Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, oth

Rev. 1.0 /Jul. 2012 44 Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.b) DQ signals

Rev. 1.0 /Jul. 2012 45 Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are used according to RD C

Rev. 1.0 /Jul. 2012 46 Table 9 - IDD5B Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.b) DQ signals are MID-L

Rev. 1.0 /Jul. 2012 47 Table 10 - IDD7 Measurement-Loop Patterna)ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loop

Rev. 1.0 /Jul. 2012 48 IDD Specifications (Tcase: 0 to 95oC)* Module IDD values in the datasheet are only a calculation based on the component IDD spe

Rev. 1.0 /Jul. 2012 49 8GB, 1G x 64 SO-DIMM: HMT41GS6MFR8CSymbol DDR3 1066 DDR3 1333 DDR3 1600 Unit noteIDD0 960 1120 1320 mAIDD1 1040 1200 1400 mAIDD

Rev. 1.0 /Jul. 2012 5 Pin DescriptionsPin Name DescriptionNumberPin Name DescriptionNumberCK[1:0] Clock Input, positive line 2 DQ[63:0] Data Input/

Rev. 1.0 /Jul. 2012 50 Module Dimensions 256Mx64 - HMT425S6MFR6CFrontBackSPD30.0mm 67.60mm20.0mm 6.002.021.00 39.002.153.00pin 1pin 203Detail-A4.00 0.

Rev. 1.0 /Jul. 2012 51 512Mx64 - HMT451S6MFR8CFrontBackSPD30.0mm 67.60mm20.0mm 6.002.021.00 39.002.153.00pin 1pin 203Detail-A3.50mm max4.00 0.101.65

Rev. 1.0 /Jul. 2012 52 1Gx64 - HMT41GS6MFR8CFrontBack30.0mm 67.60mm20.0mm 6.002.021.00 39.002.153.00pin 1pin 203Detail- ASPD3.50mm maxDetail-B4.00 0.1

Rev. 1.0 /Jul. 2012 6 Input/Output Functional DescriptionsSymbol Type Polarity FunctionCK0/CK0CK1/CK1IN Cross PointThe system clock inputs. All addres

Rev. 1.0 /Jul. 2012 7 SDA I/O —This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SD

Rev. 1.0 /Jul. 2012 8 Pin AssignmentsPin #Front SidePin #Back SidePin #Front SidePin #Back SidePin #Front SidePin #Back SidePin #Front SidePin #Back S

Rev. 1.0 /Jul. 2012 9 Functional Block Diagram2GB, 256Mx64 Module(1Rank of x16) DQS1DQS1DM1DQ [8:15]DQS0DQS0DM0DQ [0:7]LDQSLDQSLDMDQ [0:7]D0UDQSUDQSUD