Hynix HMT451U7AFR8C-PBT0 Datenblatt

Rev. 1.1 /Jul. 2013 1 240pin DDR3 SDRAM Unbuffered DIMMDDR3 SDRAMUnbuffered DIMMsBased on 4Gb A-DieHMT425U6AFR6CHMT451U6AFR8CHMT451U7AFR8CHMT41GU6AFR

Rev. 1.1 / Jul. 2013 10 On DIMM Thermal SensorThe DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal sensor

Rev. 1.1 / Jul. 2013 11 Functional Block Diagram2GB, 256Mx64 Module(1Rank of x16)DQ4DQ5DQ6DQ7DQ0DQ1DQ2DQ3I/O 0I/O 1I/O 2I/O 3D0DM0I/O 4I/O 5I/O 6I/O 7

Rev. 1.1 / Jul. 2013 12 4GB, 512Mx64 Module(1Rank of x8) Notes:1. DQ-to-I/O wiring is shown as recom-mended but may be changed.2. DQ/DQS/DQS/ODT/DM/CK

Rev. 1.1 / Jul. 2013 13 4GB, 512Mx72 Module(1Rank of x8) DQ4DQ5DQ6DQ7DQ0DQ1DQ2DQ3DMI/O 0I/O 1I/O 2I/O 3D0DM0I/O 4I/O 5I/O 6I/O 7DQ12DQ13DQ14DQ8DQ9DQ10

Rev. 1.1 / Jul. 2013 14 8GB, 1Gx64 Module(2Rank of x8)DQ4DQ5DQ6DQ7DQ0DQ1DQ2DQ3DMI/O 0I/O 1I/O 2I/O 3D0DM0D8I/O 4I/O 5I/O 6I/O 7I/O 0I/O 1I/O 2I/O 3I/O

Rev. 1.1 / Jul. 2013 15 8GB, 1Gx72 Module(2Rank of x8)DQ4DQ5DQ6DQ7DQ0DQ1DQ2DQ3I/O 1I/O 2I/O 3D0D9I/O 4I/O 5I/O 6I/O 7I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O

Rev. 1.1 / Jul. 2013 16 Absolute Maximum RatingsAbsolute Maximum DC RatingsNotes:1. Stresses greater than those listed under “Absolute Maximum Ratings

Rev. 1.1 / Jul. 2013 17 AC & DC Operating ConditionsRecommended DC Operating ConditionsNotes:1. Under all conditions, VDDQ must be less than or eq

Rev. 1.1 / Jul. 2013 18 AC & DC Input Measurement LevelsAC and DC Logic Input Levels for Single-Ended SignalsAC and DC Input Levels for Single-End

Rev. 1.1 / Jul. 2013 19 AC and DC Input Levels for Single-Ended SignalsDDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as spe

Rev. 1.1 / Jul. 2013 2 Revision HistoryRevision No. History Draft Date Remark0.1 Initial Release Jul. 20120.2 JEDEC Spec Updated Aug. 20121.0 Changed

Rev. 1.1 / Jul. 2013 20 Vref TolerancesThe dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in fig

Rev. 1.1 / Jul. 2013 21 AC and DC Logic Input Levels for Differential SignalsDifferential signal definitionDefinition of differential ac-swing and “ti

Rev. 1.1 / Jul. 2013 22 Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)Notes:1. Used to define a differential signal slew-rat

Rev. 1.1 / Jul. 2013 23 Single-ended requirements for differential signalsEach individual component of a differential signal (CK, DQS, DQSL, DQSU, CK,

Symbol ParameterDDR3-800, 1066, 1333, & 1600Unit NotesMin MaxVSEHSingle-ended high level for strobes (VDD / 2) + 0.175 Note 3 V 1,2Single-ended hi

Rev. 1.1 / Jul. 2013 25 Differential Input Cross Point VoltageTo guarantee tight setup and hold times as well as output skew parameters with respect t

Delta TFdiffDelta TRdiffVIHdiffminVILdiffmax0Differential Input Voltage (i.e. DQS-DQS; CK-CK)Rev. 1.1 / Jul. 2013 26 Slew Rate Definitions for Single-

Rev. 1.1 / Jul. 2013 27 AC & DC Output Measurement LevelsSingle Ended AC and DC Output LevelsTable below shows the output levels used for measurem

Rev. 1.1 / Jul. 2013 28 Single Ended Output Slew RateWhen the Reference load for timing measurements, output slew rate for falling and rising edges is

Rev. 1.1 / Jul. 2013 29 Differential Output Slew RateWith the reference load for timing measurements, output slew rate for falling and rising edges is

Rev. 1.1 / Jul. 2013 3 DescriptionSK hynix Unbuffered DDR3 SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are

Rev. 1.1 / Jul. 2013 30 Reference Load for AC Timing and Output Slew RateFigure Below represents the effective reference load of 25 ohms used in defin

Rev. 1.1 / Jul. 2013 31 Overshoot and Undershoot SpecificationsAddress and Control Overshoot and Undershoot Specifications Address and Control Oversho

Rev. 1.1 / Jul. 2013 32 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications Clock, Data, Strobe and Mask Overshoot and Undershoot Def

Rev. 1.1 / Jul. 2013 33 Refresh parameters by device densityNotes:1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determi

Rev. 1.1 / Jul. 2013 34 Standard Speed BinsDDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.DDR3-800 Spe

Rev. 1.1 / Jul. 2013 35 DDR3-1066 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 39.Speed Bin DDR3-1066FUnit NoteCL - nRCD

Rev. 1.1 / Jul. 2013 36 DDR3-1333 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 39.Speed Bin DDR3-1333HUnit NoteCL - nRCD

Rev. 1.1 / Jul. 2013 37 DDR3-1600 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 39.Speed Bin DDR3-1600KUnit NoteCL - nRCD

Rev. 1.1 / Jul. 2013 38 DDR3-1866 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 39.Speed Bin DDR3-1866MUnit NoteCL - nRCD

Rev. 1.1 / Jul. 2013 39 Speed Bin Table NotesAbsolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); 1. The CL setting and CWL setting result i

Rev. 1.1 / Jul. 2013 4 Key Parameters *SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed to match.Sp

Rev. 1.1 / Jul. 2013 40 Environmental ParametersNote: 1. Stress greater than those listed may cause permanent damage to the device. This is a stress r

Rev. 1.1 / Jul. 2013 41 IDD and IDDQ Specification Parameters and Test ConditionsIDD and IDDQ Measurement ConditionsIn this chapter, IDD and IDDQ meas

Rev. 1.1 / Jul. 2013 42 Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements[Note: DIMM level Output test load condition may be d

Rev. 1.1 / Jul. 2013 43 Table 1 -Timings used for IDD and IDDQ Measurement-Loop PatternsTable 2 -Basic IDD and IDDQ Measurement ConditionsSymbolDDR3-1

Rev. 1.1 / Jul. 2013 44 IDD2NPrecharge Standby CurrentCKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, A

Rev. 1.1 / Jul. 2013 45 IDD4ROperating Burst Read CurrentCKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Com

Rev. 1.1 / Jul. 2013 46 a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00Bb) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_No

Rev. 1.1 / Jul. 2013 47 Table 3 - IDD0 Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.b) DQ signals are MID-L

Rev. 1.1 / Jul. 2013 48 Table 4 - IDD1 Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, ot

Rev. 1.1 / Jul. 2013 49 Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.b) DQ signal

Rev. 1.1 / Jul. 2013 5 Pin DescriptionsPin Name Description Pin Name DescriptionA0–A15 SDRAM address bus SCL I2C serial bus clock for EEPROMBA0–BA2 SD

Rev. 1.1 / Jul. 2013 50 Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are used according to RD

Rev. 1.1 / Jul. 2013 51 Table 9 - IDD5B Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.b) DQ signals are MID-

Rev. 1.1 / Jul. 2013 52 Table 10 - IDD7 Measurement-Loop Patterna)ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loo

Rev. 1.1 / Jul. 2013 53 IDD Specifications (Tcase: 0 to 95oC)* Module IDD values in the datasheet are only a calculation based on the component IDD sp

Rev. 1.1 / Jul. 2013 54 4GB, 512M x 72 U-DIMM: HMT451U7AFR8C8GB, 1G x 64 U-DIMM: HMT41GU6AFR8CSymbol DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Unit note

Rev. 1.1 / Jul. 2013 55 8GB, 1G x 72 U-DIMM: HMT41GU7AFR8CSymbol DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Unit noteIDD0 495 513 621 639 mAIDD1 567 576

Rev. 1.1 / Jul. 2013 56 Module Dimensions256Mx64 - HMT425U6AFR6C9.5030.0017.30Max R0.702x2.50 0.10Min 1.45DETAIL-ADETAIL-B2.10 0.154x3.00 0.102x2.

Rev. 1.1 / Jul. 2013 57 512Mx64 - HMT451U6AFR8C9.5017.30Max R0.702x2.50 0.10Min 1.45DETAIL-ADETAIL-B2.10 0.154x3.00 0.102x2.30 0.105.17547.0071.0

Rev. 1.1 / Jul. 2013 58 512Mx72- HMT451U7AFR8C9.5017.30Max R0.702x2.50 0.10Min 1.45DETAIL-ADETAIL-B2.10 0.154x3.00 0.102x2.30 0.105.17547.0071.00

Rev. 1.1 / Jul. 2013 59 1Gx64 - HMT41GU6AFR8C9.5017.30Max R0.702x2.50 0.10Min 1.45DETAIL-ADETAIL-B2.10 0.154x3.00 0.102x2.30 0.105.17547.0071.001

Rev. 1.1 / Jul. 2013 6 Input/Output Functional DescriptionsSymbol Type Polarity FunctionCK0–CK1CK0–CK1SSTLDifferential crossingCK and CK are different

Rev. 1.1 / Jul. 2013 60 1Gx72 - HMT41GU7AFR8C9.5017.30Max R0.702x2.50 0.10Min 1.45DETAIL-ADETAIL-B2.10 0.154x3.00 0.102x2.30 0.105.17547.0071.001

Rev. 1.1 / Jul. 2013 7 DQS0–DQS8DQS0–DQS8SSTLDifferential crossingData strobe for input and output data.SA0–SA2 —These signals are tied at the system

Rev. 1.1 / Jul. 2013 8 Pin AssignmentsFront Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)Pin #x64Non-ECCx7

Rev. 1.1 / Jul. 2013 9 31 DQ25 DQ25 151VSSVSS91 DQ41 DQ41 211VSSVSS32VSSVSS152 DM3 DM3 92VSSVSS212 DM5 DM533 DQS3DQS3 153 NC NC 93 DQS5DQS5 213 NC NC3